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PI2EQX3231BL
3.0Gbps, 1-port, SATA2 i/m Re-Driver
Features
* * * * * * * * * * * SATA2 i, m; external SATA2 Two 3.0Gbps differential signal pairs Adjustable Receiver Equalization 100-Ohm Differential CML I/O's Independent Output Emphasis Control Input signal level detect and squelch for each channel OOB Support Low Power (100mW per Channel) Stand-by Mode - Power Down State VDD Operating Range: 1.5V to 1.8V Packaging: -- 20-TQFN (3.5x 4.5mm)
Description
Pericom Semiconductor's PI2EQX3231BL is a low power, signal Re-Driver. The device provides programmable equalization, to optimize performance over a variety of physical mediums by reducing Inter-Symbol Interference. PI2EQX3231BL supports two 100-Ohm Differential CML data I/O's between the Protocol ASIC to a switch fabric, across a backplane, or to extend the signals across other distant data pathways on the user's platform. The integrated equalization circuitry provides flexibility with signal integrity of the signal before the re-driver. A low-level input signal detection and output squelch function is provided for each channel. Each channel operates fully independantly. When the channels are enabled (CE=1) and operating, that channels input signal level (on xI+/-) determines whether the output is active. If the input signal level of the channel falls below the active threshold level (Vth-) then the outputs are driven to the common mode voltage. In addition to signal conditioning, when CE = 0, the device enters a low power standby mode.
Block Diagram
Pin Diagram (Top Side View)
A_EQ A_EM
Signal Detection
VDD
CML CML XI+ Equalizer XI - x_EQ Limiting Amp XO - XO+
AI+ AIGND VDD BO+ BOVDD
2 3 4 5 6 7 8 9
1
20
19 18 17 16 15 14 13 12
CE AO+ AOGND VDD BI+ BIGND
GND
x_EM
- Repeated 2 times -
10 11 B_EQ B_EM
CE
Power Management
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PI2EQX3231BL 3.0Gbps, 1-Port, SATA2 i/m Re-Driver
Pin Name A_EM A_EQ AI+ AIAO+ AOB_EQ B_EM BI+ BIBO+ BOCE GND VDD Type Input Input Input Output Input Input Input Output Input GND Power Description Selection pin for channel A output Emphasis adjustment. (See output Emphasis Adjustment table). With internal 50K-Ohm pull-up resistor. Selection pin for equalizer of Ain. (See Input Equalizer Adjustment table.) With internal 50K-Ohm pull-up resistor. CML input forward channel A with internal 50-Ohm pull down. CML output channel A with internal 50-Ohm pull up. Selection pin for equalizer of B_IN. (See Input Equalizer Adjustment table.) With internal 50K-Ohm pull-up resistor. Selection pin for channel B output Emphasis adjustment. (See output Emphasis Adjustment table). With internal 50K-Ohm pull-up resistor. CML input return channel B with internal 50-Ohm pull down. Positive CML output channel B with internal 50-Ohm pull up. Chip Enable "high" provides normal operation. "Low" for power down mode. With internal 50K-Ohm pull-up resistor. Supply ground. 1.5V to 1.8V supply voltage (0.1V)
Pin Description
Pin # 20 1 3 4 18 17 10 11 14 13 7 8 19 5, 12, 16, Center Pad 2,6, 9,15
Input Equalizer Adjustment
x_EQ 0 1
Compliance Channel @ 1.5 GHz 1.5dB 1.0dB 5.5dB 1.0dB
Output Emphasis Adjustment
x_EM 0 1
Compliance Channel @ 1.5GHz 0dB -3.5dB
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PI2EQX3231BL 3.0Gbps, 1-Port, SATA2 i/m Re-Driver
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.) Storage Temperature........................................................ -65C to +150C Supply Voltage to Ground Potential ................................... -0.5V to +2.5V DC SIG Voltage ..........................................................-0.5V to VDD +0.5V Current Output ................................................................-25mA to +25mA Power Dissipation Continous ......................................................... 500mW Operating Temperature .............................................................. 0 to +70C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
AC/DC Electrical Characteristics (VDD = 1.4V to 1.9V)
Symbol IDD Pstandby Pactive18 Pidle18 Pactive15 Pidle15
tpd
Parameter Power Supply Current Power, standby Power, active @ 1.8V Power, idle @ 1.8V Power, active @ 1.5V Power, idle @ 1.5V Latency
Conditions EN_[A:B] = 0 VDD=1.8V, EN_[A:B] = 1, Vrx-diff-p >= Vth-sd VDD=1.8V, EN_[A:B] = 1, Vrx-diff-p < Vth-sd VDD=1.5V, EN_[A:B] = 1, Vrx-diff-p >= Vth-sd VDD=1.5V, EN_[A:B] = 1, Vrx-diff-p < Vth-sd From differential input to differential output
Min.
Typ.
125 100 100 80 2.0
Max. 90 1 160
Units mA mW mW
130
mW mW ns
CML Receiver Input Differential Input Peak-toVRX-DIFFP-P peak Voltage AC Peak Common Mode VRX-CM-ACP Input Voltage VTH-SD Signal detect Threshold ZRX-DC DC Input Impedance DC Differential Input ZRX-DIFF-DC Impedance Equalization JRS Residual Jitter(1,2) JRM Random Jitter(1,2)
0.200 150 CE = 1 50(2) 40 80 50 100
V mV
200 (3) mVppd 60 Ohm 120
Total Jitter 1.5
0.3
Ulp-p psrms
Notes 1. K28.7 pattern is applied differentially at point A as shown in Figure 1. 2. Total jitter does not include the signal source jitter. Total jitter (TJ) = (14.1 x RJ + DJ) where RJ is random RMS jitter and DJ is maximum deterministic jitter. Signal source is a K28.5 pattern (00 1111 1010 11 0000 0101) for the deterministic jitter test and K28.7 (0011111000) or equivalent for random jitter test. Residual jitter is that which remains after equalizing media-induced losses of the environment of Figure 1 or its equivalent. The deterministic jitter at point B must be from media-induced loss, and not from clock source modulation. JItter is measured at 0V at point C of Figure 1. 3. Using Compliance test at 1.5Gbps and 3Gbps. Also using OOB (OOB is formed by ALIGNp primitive or D24.3) test patterns at 1.5Gbps. The ALIGN primitive (K28.5+D10.2+D27.3 = 0011111010+0101010101+0010011100). The D24.3 = 00110011001100110011
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PI2EQX3231BL 3.0Gbps, 1-Port, SATA2 i/m Re-Driver
AC/DC Electrical Characteristics
Symbol Parameter Conditions Min. Typ. Max. Units CML Transmitter Output (100 differential) VTX-DIFFP-P VTX-C tF, tR ZTX-DIFF-DC VIH VIL IIH IIL Differential Peak-to-peak Ouput Voltage Common-Mode Voltage Transition Time DC Differential TX Impedance VTX-DIFFP-P = 2 * | VTX-D+ - VTX-D- | | VTX-D+ + VTX-D-|/2 20% to 80%(1) 80 100 400 VDD - 0.3 150 120 600 mV V ps Ohm
LVCMOS Control Pins Input High Voltage Input Low Voltage Input High Current Input Low Current 0.65 x VDD 0.35 x VDD 5 100 V
A
Note: 1. When S_ES=0 select SATAx standard, When S_ES=1 select SATAi/m standard
FR4
Signal Source A B D.U.T. SmA Connector 30IN SmA Connector C
In
Out
Figure 1. Test Condition Referenced in the Electrical Characteristic Table
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PI2EQX3231BL 3.0Gbps, 1-Port, SATA2 i/m Re-Driver
Packaging Mechanical: 20-contact TQFN (ZH)
DATE: 03/14/08 DESCRIPTION: 20-Contact, Very Thin Quad Flat No-Lead, TQFN PACKAGE CODE: ZH20 DOCUMENT CONTROL #: PD-2032
08 0122
REVISION: A
Ordering Information
Ordering Number PI2EQX3231BLZHE Package Code ZH Package Description Pb-Free and Green 20-contact TQFN
Notes: * Thermal characteristics can be found on the company web site at www.pericom.com/packaging/ * E = Pb-free and Green * X suffix = Tape/Reel
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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